000 03574nam a22005055i 4500
001 978-94-007-7663-0
003 DE-He213
005 20140220082532.0
007 cr nn 008mamaa
008 131018s2014 ne | s |||| 0|eng d
020 _a9789400776630
_9978-94-007-7663-0
024 7 _a10.1007/978-94-007-7663-0
_2doi
050 4 _aQC610.9-611.8
072 7 _aTJFD5
_2bicssc
072 7 _aTEC008090
_2bisacsh
082 0 4 _a537.622
_223
100 1 _aFranco, Jacopo.
_eauthor.
245 1 0 _aReliability of High Mobility SiGe Channel MOSFETs for Future CMOS Applications
_h[electronic resource] /
_cby Jacopo Franco, Ben Kaczer, Guido Groeseneken.
264 1 _aDordrecht :
_bSpringer Netherlands :
_bImprint: Springer,
_c2014.
300 _aXIX, 187 p. 219 illus.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aSpringer Series in Advanced Microelectronics,
_x1437-0387 ;
_v47
505 0 _a1 Introduction -- 2 Degradation mechanisms -- 3 Techniques and devices -- 4 Negative Bias Temperature Instability in (Si)Ge pMOSFETs -- 5 Negative Bias Temperature Instability in nanoscale devices -- 6 Channel Hot Carriers and other reliability mechanisms -- 7 Conclusions and perspectives.
520 _aDue to the ever increasing electric fields in scaled CMOS devices, reliability is becoming a showstopper for further scaled technology nodes. Although several groups have already demonstrated functional Si channel devices with aggressively scaled Equivalent Oxide Thickness (EOT) down to 5Å, a 10 year reliable device operation cannot be guaranteed anymore due to severe Negative Bias Temperature Instability. This book focuses on the reliability of the novel (Si)Ge channel quantum well pMOSFET technology. This technology is being considered for possible implementation in next CMOS technology nodes, thanks to its benefit in terms of carrier mobility and device threshold voltage tuning. We observe that it also opens a degree of freedom for device reliability optimization. By properly tuning the device gate stack, sufficiently reliable ultra-thin EOT devices with a 10 years lifetime at operating conditions are demonstrated. The extensive experimental datasets collected on a variety of processed 300mm wafers and presented here show the reliability improvement to be process- and architecture-independent and, as such, readily transferable to advanced device architectures as Tri-Gate (finFET) devices. We propose a physical model to understand the intrinsically superior reliability of the MOS system consisting of a Ge-based channel and a SiO2/HfO2 dielectric stack. The improved reliability properties here discussed strongly support (Si)Ge technology as a clear frontrunner for future CMOS technology nodes.
650 0 _aPhysics.
650 0 _aSystems engineering.
650 0 _aOptical materials.
650 1 4 _aPhysics.
650 2 4 _aSemiconductors.
650 2 4 _aCircuits and Systems.
650 2 4 _aOptical and Electronic Materials.
650 2 4 _aElectronic Circuits and Devices.
700 1 _aKaczer, Ben.
_eauthor.
700 1 _aGroeseneken, Guido.
_eauthor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9789400776623
830 0 _aSpringer Series in Advanced Microelectronics,
_x1437-0387 ;
_v47
856 4 0 _uhttp://dx.doi.org/10.1007/978-94-007-7663-0
912 _aZDB-2-ENG
999 _c94093
_d94093