000			01784nam a22004815i 4500
001			978-3-540-95948-9
003			DE-He213
005			20130515021842.0
007			cr nn 008mamaa
008			100301s2009 gw | s |||| 0|eng d
020			_a9783540959489 _9978-3-540-95948-9
024	7		_a10.1007/978-3-540-95948-9 _2doi
050		4	_aQA76.9.L63
072		7	_aUYF _2bicssc
072		7	_aCOM036000 _2bisacsh
082	0	4	_a621.395 _223
100	1		_aSvensson, Lars.
245	1	0	_aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation _h[electronic resource] : _b18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers / _cedited by Lars Svensson, José Monteiro.
260			_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg, _c2009.
300			_bdigital.
490	0		_aLecture Notes in Computer Science, _x0302-9743 ; _v5349
650		0	_aComputer science.
650		0	_aMemory management (Computer science).
650		0	_aLogic design.
650		0	_aComputer system performance.
650		0	_aSystems engineering.
650	1	4	_aComputer Science.
650	2	4	_aLogic Design.
650	2	4	_aProcessor Architectures.
650	2	4	_aSystem Performance and Evaluation.
650	2	4	_aArithmetic and Logic Structures.
650	2	4	_aMemory Structures.
650	2	4	_aCircuits and Systems.
700	1		_aMonteiro, José.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9783540959472
830		0	_aLecture Notes in Computer Science, _x0302-9743 ; _v5349
856	4	0	_uhttp://dx.doi.org/10.1007/978-3-540-95948-9
912			_aZDB-2-SCS
912			_aZDB-2-LNC
999			_c81389 _d81389