000 01280nam a22003855i 4500
001 978-1-4419-9359-5
003 DE-He213
005 20130515021104.0
007 cr nn 008mamaa
008 110517s2011 xxu| s |||| 0|eng d
020 _a9781441993595
_9978-1-4419-9359-5
024 7 _a10.1007/978-1-4419-9359-5
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aKundu, Sudipta.
245 1 0 _aHigh-Level Verification
_h[electronic resource] :
_bMethods and Tools for Verification of System-Level Designs /
_cby Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta.
260 _aNew York, NY :
_bSpringer New York,
_c2011.
300 _bdigital.
650 0 _aEngineering.
650 0 _aComputer aided design.
650 0 _aSystems engineering.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aComputer-Aided Engineering (CAD, CAE) and Design.
700 1 _aLerner, Sorin.
700 1 _aGupta, Rajesh K.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9781441993588
856 4 0 _uhttp://dx.doi.org/10.1007/978-1-4419-9359-5
912 _aZDB-2-ENG
999 _c73598
_d73598