000			01446nam a22004455i 4500
001			978-1-4020-4758-9
003			DE-He213
005			20130515020756.0
007			cr nn 008mamaa
008			100301s2006 ne | s |||| 0|eng d
020			_a9781402047589 _9978-1-4020-4758-9
024	7		_a10.1007/978-1-4020-4758-9 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aDasGupta, Pallab.
245	1	2	_aA Roadmap for Formal Property Verification _h[electronic resource] / _cby Pallab DasGupta.
260			_aDordrecht : _bSpringer Netherlands, _c2006.
300			_bdigital.
650		0	_aEngineering.
650		0	_aLogic design.
650		0	_aComputer science.
650		0	_aComputer aided design.
650		0	_aElectronics.
650		0	_aSystems engineering.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aComputer-Aided Engineering (CAD, CAE) and Design.
650	2	4	_aElectronics and Microelectronics, Instrumentation.
650	2	4	_aLogic Design.
650	2	4	_aElectronic and Computer Engineering.
650	2	4	_aMathematical Logic and Formal Languages.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781402047572
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4020-4758-9
912			_aZDB-2-ENG
999			_c69974 _d69974