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001 978-90-481-8540-5
003 DE-He213
005 20140220084600.0
007 cr nn 008mamaa
008 100316s2010 ne | s |||| 0|eng d
020 _a9789048185405
_9978-90-481-8540-5
024 7 _a10.1007/978-90-481-8540-5
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aHuang, Chao.
_eeditor.
245 1 0 _aRobust Computing with Nano-scale Devices
_h[electronic resource] :
_bProgresses and Challenges /
_cedited by Chao Huang.
264 1 _aDordrecht :
_bSpringer Netherlands :
_bImprint: Springer,
_c2010.
300 _aVIII, 200p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aLecture Notes in Electrical Engineering,
_x1876-1100 ;
_v58
505 0 _aFault Tolerant Nanocomputing -- Transistor-Level Based Defect-Tolerance for Reliable Nanoelectronics -- Fault-Tolerant Design for Nanowire-Based Programmable Logic Arrays -- Built-In Self-Test and Defect Tolerance for Molecular Electronics-Based NanoFabrics -- The Prospect and Challenges of CNFET Based Circuits: A Physical Insight -- Computing with Nanowires: A Self Assembled Neuromorphic Architecture -- Computational Opportunities and CAD for Nanotechnologies.
520 _aAlthough complementary metal-oxide semiconductor (CMOS) technology will continue dominating the digital electronic circuits for the next 10-15 years, a number of grand challenges have emerged as the transistor size scales down. The rising costs of semiconductor mask and fabrication pose economic barriers to lithography. The quantum effects and increasing leakage power begin setting physical limits on continuous CMOS feature size shrinking. The research advances of innovative nano-scale devices have created great opportunities to surpass the barriers faced by CMOS technology, which include nanowires, carbon nanotube transistors, programmable molecular switches, resonant tunneling diodes, quantum dots, etc. However, the success of many nanotechnologies relies on the self-assembly fabrication process to fabricate circuits. The stochastic self-assembly fabrication, unfortunately, has low reliability with defect densities several orders of magnitude higher than conventional CMOS technology. Robust Nano-Computing focuses on various issues of robust nano-computing, defect-tolerance design for nano-technology at different design abstraction levels. It addresses both redundancy- and configuration-based methods as well as fault detecting techniques through the development of accurate computation models and tools. The contents present an insightful view of the ongoing researches on nano-electronic devices, circuits, architectures, and design methods, as well as provide promising directions for future research.
650 0 _aEngineering.
650 0 _aComputer science.
650 0 _aElectronic data processing.
650 0 _aSystems engineering.
650 0 _aNanotechnology.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aNanotechnology.
650 2 4 _aProcessor Architectures.
650 2 4 _aComputing Methodologies.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9789048185399
830 0 _aLecture Notes in Electrical Engineering,
_x1876-1100 ;
_v58
856 4 0 _uhttp://dx.doi.org/10.1007/978-90-481-8540-5
912 _aZDB-2-ENG
999 _c113480
_d113480