| 000 | 03033nam a22004695i 4500 | ||
|---|---|---|---|
| 001 | 978-90-481-3443-4 | ||
| 003 | DE-He213 | ||
| 005 | 20140220084558.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 100301s2010 ne | s |||| 0|eng d | ||
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_a9789048134434 _9978-90-481-3443-4 |
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| 024 | 7 |
_a10.1007/978-90-481-3443-4 _2doi |
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| 050 | 4 | _aTK7888.4 | |
| 072 | 7 |
_aTJFC _2bicssc |
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| 072 | 7 |
_aTEC008010 _2bisacsh |
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| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aHong, Dongwoo. _eauthor. |
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| 245 | 1 | 0 |
_aEfficient Test Methodologies for High-Speed Serial Links _h[electronic resource] / _cby Dongwoo Hong, Kwang-Ting Cheng. |
| 264 | 1 |
_aDordrecht : _bSpringer Netherlands, _c2010. |
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| 300 |
_aXII, 98p. _bonline resource. |
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| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
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| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
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| 490 | 1 |
_aLecture Notes in Electrical Engineering, _x1876-1100 ; _v51 |
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| 505 | 0 | _aAn Efficient Jitter Measurement Technique -- BER Estimation for Linear Clock and Data Recovery Circuit -- BER Estimation for Non-linear Clock and Data Recovery Circuit -- Gaps in Timing Margining Test -- An Accurate Jitter Estimation Technique -- A Two-Tone Test Method for Continuous-Time Adaptive Equalizers -- Conclusions. | |
| 520 | _aWith the increasing demand for higher data bandwidth, communication systems’ data rates have reached the multi-gigahertz range and even beyond. Advances in semiconductor technologies have accelerated the adoption of high-speed serial interfaces, such as PCI-Express, Serial-ATA, and XAUI, in order to mitigate the high pin-count and the data-channel skewing problems. However, with the increasing number of I/O pins and greater data rates, significant challenges arise for testing high-speed interfaces in terms of test cost and quality, especially in high volume manufacturing (HVM) environments. Efficient Test Methodologies for High-Speed Serial Links describes in detail several new and promising techniques for cost-effectively testing high-speed interfaces with a high test coverage. One primary focus of Efficient Test Methodologies for High-Speed Serial Links is on efficient testing methods for jitter and bit-error-rate (BER), which are widely used for quantifying the quality of a communication system. Various analysis as well as experimental results are presented to demonstrate the validity of the presented techniques. | ||
| 650 | 0 | _aEngineering. | |
| 650 | 0 | _aComputer science. | |
| 650 | 0 | _aSystems engineering. | |
| 650 | 1 | 4 | _aEngineering. |
| 650 | 2 | 4 | _aCircuits and Systems. |
| 650 | 2 | 4 | _aRegister-Transfer-Level Implementation. |
| 700 | 1 |
_aCheng, Kwang-Ting. _eauthor. |
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| 710 | 2 | _aSpringerLink (Online service) | |
| 773 | 0 | _tSpringer eBooks | |
| 776 | 0 | 8 |
_iPrinted edition: _z9789048134427 |
| 830 | 0 |
_aLecture Notes in Electrical Engineering, _x1876-1100 ; _v51 |
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| 856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/978-90-481-3443-4 |
| 912 | _aZDB-2-ENG | ||
| 999 |
_c113353 _d113353 |
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