000			02951nam a22004815i 4500
001			978-1-4419-0959-6
003			DE-He213
005			20140220084504.0
007			cr nn 008mamaa
008			100301s2010 xxu| s |||| 0|eng d
020			_a9781441909596 _9978-1-4419-0959-6
024	7		_a10.1007/978-1-4419-0959-6 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aLin, Youn-Long Steve. _eauthor.
245	1	0	_aVLSI Design for Video Coding _h[electronic resource] : _bH.264/AVC Encoding from Standard Specification to Chip / _cby Youn-Long Steve Lin, Chao-Yang Kao, Hung-Chih Kuo, Jian-Wen Chen.
250			_a1st.
264		1	_aBoston, MA : _bSpringer US, _c2010.
300			_aXI, 176p. 308 illus., 154 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_ato Video Coding and H.264/AVC -- Intra Prediction -- Integer Motion Estimation -- Fractional Motion Estimation -- Motion Compensation -- Transform Coding -- Deblocking Filter -- CABAC Encoder -- System Integration.
520			_aBack Cover Copy VLSI Design for Video Coding By: Youn-Long Lin Chao-Yang Kao Jian-Wen Chen Hung-Chih Kuo High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing. This book presents VLSI architectural design and chip implementation for high definition H.264/AVC video encoding with a complete FPGA prototype. It serves as an invaluable reference for anyone interested in VLSI design for video coding. • Presents state-of-the-art VLSI architectural design and chip implementation for high definition H.264/AVC video encoding; • Employs massively parallel processing to deliver 1080pHD, with efficient design that can be prototyped via FPGA; • Every subsystem is presented from standard specification, algorithmic description, design considerations, timing planning, block diagram to test-bench verification;
650		0	_aEngineering.
650		0	_aComputer aided design.
650		0	_aSystems engineering.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aComputer-Aided Engineering (CAD, CAE) and Design.
700	1		_aKao, Chao-Yang. _eauthor.
700	1		_aKuo, Hung-Chih. _eauthor.
700	1		_aChen, Jian-Wen. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781441909589
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4419-0959-6
912			_aZDB-2-ENG
999			_c110285 _d110285