000			03503nam a22004575i 4500
001			978-1-4419-0928-2
003			DE-He213
005			20140220084503.0
007			cr nn 008mamaa
008			110414s2010 xxu| s |||| 0|eng d
020			_a9781441909282 _9978-1-4419-0928-2
024	7		_a10.1007/978-1-4419-0928-2 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aGirard, Patrick. _eeditor.
245	1	0	_aPower-Aware Testing and Test Strategies for Low Power Devices _h[electronic resource] / _cedited by Patrick Girard, Nicola Nicolici, Xiaoqing Wen.
264		1	_aBoston, MA : _bSpringer US, _c2010.
300			_aXXII, 353p. 444 illus., 222 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aFundamentals of VLSI Testing -- Power Issues During Test -- Low-Power Test Pattern Generation -- Power-Aware Design-for-Test -- Power-Aware Test Data Compression and BIST -- Power-Aware System-Level Test Planning -- Low-Power Design Techniques and Test Implications -- Test Strategies for Multivoltage Designs -- Test Strategies for Gated Clock Designs -- Test of Power Management Structures -- EDA Solution for Power-Aware Design-for-Test.
520			_aPower-Aware Testing and Test Strategies for Low-Power Devices Edited by: Patrick Girard, Research Director, CNRS / LIRMM, France Nicola Nicolici, Associate Professor, McMaster University, Canada Xiaoqing Wen, Professor, Kyushu Institute of Technology, Japan Managing the power consumption of circuits and systems is now considered as one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low-power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and Electronic Design Automation (EDA) solutions for testing low-power devices. The first comprehensive book on power-aware test for (low-power) circuits and systems Shows readers how low-power devices can be tested safely without affecting yield and reliability Includes necessary background information on design-for-test and low-power design Covers in detail power-constrained test techniques, including power-aware automatic test pattern generation, design-for-test, built-in self-test and test compression Presents state-of-the-art industrial practices and EDA solutions
650		0	_aEngineering.
650		0	_aComputer aided design.
650		0	_aSystems engineering.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aComputer-Aided Engineering (CAD, CAE) and Design.
700	1		_aNicolici, Nicola. _eeditor.
700	1		_aWen, Xiaoqing. _eeditor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781441909275
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4419-0928-2
912			_aZDB-2-ENG
999			_c110276 _d110276