| 000 | 02810nam a22005055i 4500 | ||
|---|---|---|---|
| 001 | 978-90-481-9591-6 | ||
| 003 | DE-He213 | ||
| 005 | 20140220083825.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 110126s2011 ne | s |||| 0|eng d | ||
| 020 |
_a9789048195916 _9978-90-481-9591-6 |
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| 024 | 7 |
_a10.1007/978-90-481-9591-6 _2doi |
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| 050 | 4 | _aTK7888.4 | |
| 072 | 7 |
_aTJFC _2bicssc |
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| 072 | 7 |
_aTEC008010 _2bisacsh |
|
| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aKahng, Andrew B. _eauthor. |
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| 245 | 1 | 0 |
_aVLSI Physical Design: From Graph Partitioning to Timing Closure _h[electronic resource] / _cby Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu. |
| 264 | 1 |
_aDordrecht : _bSpringer Netherlands, _c2011. |
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| 300 |
_aXII, 310 p. 150 illus. _bonline resource. |
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| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
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| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
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| 520 | _aDesign and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact. VLSI Physical Design: From Graph Partitioning to Timing Closure introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure. | ||
| 650 | 0 | _aEngineering. | |
| 650 | 0 | _aLogic design. | |
| 650 | 0 | _aComputer aided design. | |
| 650 | 0 | _aElectronics. | |
| 650 | 0 | _aSystems engineering. | |
| 650 | 1 | 4 | _aEngineering. |
| 650 | 2 | 4 | _aCircuits and Systems. |
| 650 | 2 | 4 | _aLogic Design. |
| 650 | 2 | 4 | _aElectronics and Microelectronics, Instrumentation. |
| 650 | 2 | 4 | _aComputer-Aided Engineering (CAD, CAE) and Design. |
| 700 | 1 |
_aLienig, Jens. _eauthor. |
|
| 700 | 1 |
_aMarkov, Igor L. _eauthor. |
|
| 700 | 1 |
_aHu, Jin. _eauthor. |
|
| 710 | 2 | _aSpringerLink (Online service) | |
| 773 | 0 | _tSpringer eBooks | |
| 776 | 0 | 8 |
_iPrinted edition: _z9789048195909 |
| 856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/978-90-481-9591-6 |
| 912 | _aZDB-2-ENG | ||
| 999 |
_c109044 _d109044 |
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