000			03314nam a22004575i 4500
001			978-1-4419-7418-1
003			DE-He213
005			20140220083723.0
007			cr nn 008mamaa
008			101110s2011 xxu| s |||| 0|eng d
020			_a9781441974181 _9978-1-4419-7418-1
024	7		_a10.1007/978-1-4419-7418-1 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aBhunia, Swarup. _eeditor.
245	1	0	_aLow-Power Variation-Tolerant Design in Nanometer Silicon _h[electronic resource] / _cedited by Swarup Bhunia, Saibal Mukhopadhyay.
250			_a1.
264		1	_aBoston, MA : _bSpringer US, _c2011.
300			_aX, 240p. 100 illus. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aIntroduction and Motivation -- Background on Power Dissipation -- Background on Parameter Variations -- Low power Logic Design under Variations -- Low Power Memory Design under Variations -- System and Architecture Level Design -- Emerging Challenges and Solution Approach -- Conclusion and Discussion.
520			_aLow-Power Variation-Tolerant Design in Nanometer Silicon Edited by: Swarup Bhunia Saibal Mukhopadhyay Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. Coverage includes logic and memory design, modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. •Introduces readers to some of the most important challenges in low-power and variation-tolerant IC design in nanoscale technologies; •Presents a holistic view of Low-Power Variation-Tolerant Design, at different levels of design abstraction, starting from device to circuit, architecture and system; •Offers comprehensive coverage of modeling, analysis and design methodology for low power and variation-tolerant logic circuits, memory and systems, micro-architecture, DSP, mixed-signal and FPGAs, including current industrial practices, technology scaling trends, and emerging challenges; •Describes in detail modeling and analysis of different variation effects (die-to-die and within-die, process and temporal) on low-power designs; Includes coverage of ultra low-power and robust sub-threshold design.
650		0	_aEngineering.
650		0	_aComputer aided design.
650		0	_aSystems engineering.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aComputer-Aided Engineering (CAD, CAE) and Design.
700	1		_aMukhopadhyay, Saibal. _eeditor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781441974174
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4419-7418-1
912			_aZDB-2-ENG
999			_c105761 _d105761