000 02940nam a22004335i 4500
001 978-1-4419-6460-1
003 DE-He213
005 20140220083721.0
007 cr nn 008mamaa
008 101125s2011 xxu| s |||| 0|eng d
020 _a9781441964601
_9978-1-4419-6460-1
024 7 _a10.1007/978-1-4419-6460-1
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aHübner, Michael.
_eeditor.
245 1 0 _aMultiprocessor System-on-Chip
_h[electronic resource] :
_bHardware Design and Tool Integration /
_cedited by Michael Hübner, Jürgen Becker.
264 1 _aNew York, NY :
_bSpringer New York,
_c2011.
300 _aX, 300p. 100 illus.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
520 _aImproving future electronic system performance can only be achieved by exploiting parallelism on all system levels. Multicore architectures offer a better performance/Watt ratio than single core architectures with similar performance. Combining multicore and coprocessor technology promises extreme computing power for highly CPU-time-consuming applications. FPGA-based accelerators not only offer the opportunity to speed up an application by implementing their compute-intensive kernels into hardware, but also to adapt to the dynamical behavior of an application. This book describes strategies for future system design in multiprocessor system-on-chip (MPSoC) architectures. Both hardware design and integration of new development tools are discussed. Novel trends in MPSoC design, combined with reconfigurable architectures are a main topic of concern. The main emphasis is on architectures, design-flow, tool-development, applications and system design. This book deals with key issues such as on-chip communication architectures, integration of reconfigurable hardware, and physical design of multiprocessor systems. •Provides a state-of-the-art overview of system design using MPSoC architectures; •Describes current trends in on-chip communication architectures; •Offers extensive coverage of system design integrating MPSoC architectures with reconfigurable hardware; •Includes coverage of challenges in physical design for multi- and manycore hardware architectures.
650 0 _aEngineering.
650 0 _aComputer aided design.
650 0 _aSystems engineering.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aComputer-Aided Engineering (CAD, CAE) and Design.
700 1 _aBecker, Jürgen.
_eeditor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9781441964595
856 4 0 _uhttp://dx.doi.org/10.1007/978-1-4419-6460-1
912 _aZDB-2-ENG
999 _c105610
_d105610