000			04147nam a22005055i 4500
001			978-94-007-2345-0
003			DE-He213
005			20140220083341.0
007			cr nn 008mamaa
008			111028s2012 ne | s |||| 0|eng d
020			_a9789400723450 _9978-94-007-2345-0
024	7		_a10.1007/978-94-007-2345-0 _2doi
050		4	_aTK7867-7867.5
072		7	_aTJFC _2bicssc
072		7	_aTJFD5 _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aTeichmann, Philip. _eauthor.
245	1	0	_aAdiabatic Logic _h[electronic resource] : _bFuture Trend and System Level Perspective / _cby Philip Teichmann.
264		1	_aDordrecht : _bSpringer Netherlands, _c2012.
300			_aXVIII, 166 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aSpringer Series in Advanced Microelectronics, _x1437-0387 ; _v34
520			_aAdiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. Future development like the evolutionary shrinking of the minimum feature size as well as revolutionary novel transistor concepts will change the gate level savings gained by adiabatic logic. In addition, the impact of worsening degradation effects has to be considered in the design of adiabatic circuits. The impact of the technology trends on the figures of merit of adiabatic logic, energy saving potential and optimum operating frequency, are investigated, as well as degradation related issues. Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Major interest also lies on the efficient generation of the applied power-clock signal. This oscillating power supply can be used to save energy in short idle times by disconnecting circuits. An efficient way to generate the power-clock is by means of the synchronous 2N2P LC oscillator, which is also robust with respect to pattern-induced capacitive variations. An easy to implement but powerful power-clock gating supplement is proposed by gating the synchronization signals. Diverse implementations to shut down the system are presented and rated for their applicability and other aspects like energy reduction capability and data retention. Advantageous usage of adiabatic logic requires compact and efficient arithmetic structures. A broad variety of adder structures and a Coordinate Rotation Digital Computer are compared and rated according to energy consumption and area usage, and the resulting energy saving potential against static CMOS proves the ultra-low-power capability of adiabatic logic. In the end, a new circuit topology has to compete with static CMOS also in productivity. On a 130nm test chip, a large scale test vehicle containing an FIR filter was implemented in adiabatic logic, utilizing a standard, library-based design flow, fabricated, measured and compared to simulations of a static CMOS counterpart, with measured saving factors compliant to the values gained by simulation. This leads to the conclusion that adiabatic logic is ready for productive design due to compatibility not only to CMOS technology, but also to electronic design automation (EDA) tools developed for static CMOS system design.
650		0	_aPhysics.
650		0	_aLogic design.
650		0	_aElectronics.
650		0	_aSystems engineering.
650	1	4	_aPhysics.
650	2	4	_aElectronic Circuits and Devices.
650	2	4	_aCircuits and Systems.
650	2	4	_aLogic Design.
650	2	4	_aElectronics and Microelectronics, Instrumentation.
650	2	4	_aEnergy Efficiency (incl. Buildings).
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9789400723443
830		0	_aSpringer Series in Advanced Microelectronics, _x1437-0387 ; _v34
856	4	0	_uhttp://dx.doi.org/10.1007/978-94-007-2345-0
912			_aZDB-2-ENG
999			_c104453 _d104453