000 03111nam a22004695i 4500
001 978-3-642-27657-6
003 DE-He213
005 20140220083309.0
007 cr nn 008mamaa
008 120328s2012 gw | s |||| 0|eng d
020 _a9783642276576
_9978-3-642-27657-6
024 7 _a10.1007/978-3-642-27657-6
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aVingron, Shimon P.
_eauthor.
245 1 0 _aLogic Circuit Design
_h[electronic resource] :
_bSelected Methods /
_cby Shimon P. Vingron.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c2012.
300 _aXIV, 258p. 207 illus.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aLogic Variables, Logic Formulas, Karnaugh Maps, Reduced Karnaugh Maps -- Tautologies, Propositional Logic -- Canonical and Shegalkin Normal Forms, Minimising Logic Functions, Composition of Circuits -- Theory of Latches, Automata Models, Asynchronous Sequential Circuits, Verifying a Sequential Design.
520 _a    In three main divisions the  book covers combinational circuits, latches, and asynchronous sequential circuits. Combinational circuits have  no memorising ability, while sequential circuits have such an ability to various degrees. Latches are the simplest sequential circuits, ones with the shortest memory. The presentation is decidedly non-standard.         The design of combinational circuits is discussed in an orthodox manner using normal forms and in an unorthodox manner using set-theoretical evaluation formulas relying heavily on Karnaugh maps. The latter approach allows for a new design technique called composition.          Latches are covered very extensively. Their memory functions are expressed mathematically in a time-independent manner allowing the use of (normal, non-temporal) Boolean logic in their calculation. The theory of latches is then used as the basis for calculating asynchronous circuits.         Asynchronous circuits are specified in a tree-representation, each internal node of the tree representing an internal latch of the circuit, the latches specified by the tree itself. The tree specification allows solutions of formidable problems such as algorithmic state assignment, finding equivalent states non-recursively, and verifying asynchronous circuits.
650 0 _aEngineering.
650 0 _aLogic design.
650 0 _aMathematics.
650 0 _aSystems engineering.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aLogic Design.
650 2 4 _aElectronic Circuits and Devices.
650 2 4 _aInformation and Communication, Circuits.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783642276569
856 4 0 _uhttp://dx.doi.org/10.1007/978-3-642-27657-6
912 _aZDB-2-ENG
999 _c102648
_d102648