000 03162nam a22004695i 4500
001 978-1-4614-2296-9
003 DE-He213
005 20140220083245.0
007 cr nn 008mamaa
008 120307s2012 xxu| s |||| 0|eng d
020 _a9781461422969
_9978-1-4614-2296-9
024 7 _a10.1007/978-1-4614-2296-9
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aOnabajo, Marvin.
_eauthor.
245 1 0 _aAnalog Circuit Design for Process Variation-Resilient Systems-on-a-Chip
_h[electronic resource] /
_cby Marvin Onabajo, Jose Silva-Martinez.
264 1 _aBoston, MA :
_bSpringer US,
_c2012.
300 _aXI, 187p. 125 illus.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aIntroduction -- Process Variation Challenges and Solutions Approaches -- High-Linearity Transconductance Amplifiers with Digital Correction Capability -- Multi-Bit Quantizer Design for Continuous-Time Sigma-Delta Modulators with Reduced Device Matching Requirements -- An On-Chip Temperature Sensor for the Measurement of RF Power Dissipation and Thermal Gradients -- Mismatch Reduction for Transitiors in High-Frequency Differential Analog Signal Paths -- Summary and Conclusions.
520 _aThis book describes several techniques to address variation-related design challenges for analog blocks in mixed-signal systems-on-chip. The methods presented are results from recent research works involving receiver front-end circuits, baseband filter linearization, and data conversion. These circuit-level techniques are described, with their relationships to emerging system-level calibration approaches, to tune the performances of analog circuits with digital assistance or control. Coverage also includes a strategy to utilize on-chip temperature sensors to measure the signal power and linearity characteristics of analog/RF circuits, as demonstrated by test chip measurements.    Describes a variety of variation-tolerant analog circuit design examples, including from RF front-ends, high-performance ADCs and baseband filters; Includes built-in testing techniques, linked to current industrial trends; Balances digitally-assisted performance tuning with analog performance tuning and mismatch reduction approaches; Describes theoretical concepts as well as experimental results for test chips designed with variation-aware techniques.
650 0 _aEngineering.
650 0 _aComputer science.
650 0 _aElectronics.
650 0 _aSystems engineering.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aElectronics and Microelectronics, Instrumentation.
650 2 4 _aProcessor Architectures.
700 1 _aSilva-Martinez, Jose.
_eauthor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9781461422952
856 4 0 _uhttp://dx.doi.org/10.1007/978-1-4614-2296-9
912 _aZDB-2-ENG
999 _c101252
_d101252