000			03107nam a22004575i 4500
001			978-1-4614-0962-5
003			DE-He213
005			20140220083240.0
007			cr nn 008mamaa
008			111117s2012 xxu| s |||| 0|eng d
020			_a9781461409625 _9978-1-4614-0962-5
024	7		_a10.1007/978-1-4614-0962-5 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aYu, Qiaoyan. _eauthor.
245	1	0	_aTransient and Permanent Error Control for Networks-on-Chip _h[electronic resource] / _cby Qiaoyan Yu, Paul Ampadu.
264		1	_aNew York, NY : _bSpringer New York, _c2012.
300			_aXII, 160 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aIntroduction -- Existing Transient and Permanent Error Management in NoCs -- Adaptive Error Control Coding at Datalink Layer -- Transient and Permanent Link Errors Co-Management -- Dual-Layer Cooperative Error Control for Transient Error -- A Flexible Parallel Simulator for Networks-on-Chip with Error Control -- Conclusions and Future Directions. .
520			_aThis book addresses reliability and energy efficiency of on-chip networks using a configurable error control coding (ECC) scheme for datalink-layer transient error management. The method can adjust both error detection and correction strengths at runtime by varying the number of redundant wires for parity-check bits. Methods are also presented to tackle joint transient and permanent error correction, exploiting the redundant resources already available on-chip. A parallel and flexible network simulator is also introduced, which facilitates examining the impact of various error control methods on network-on-chip performance. Includes a complete survey of error control methods for reliable networks-on-chip, evaluated for reliability, energy and performance metrics; Provides analysis of error control in various network-on-chip layers, as well as presentation of an innovative multi-layer error control coding technique; Presents state-of-the-art solutions to address simultaneously reliability, energy and performance; Describes configurable error management solutions and their hardware implementation details for variable noise conditions; Provides details of a flexible and parallel NoC simulator and corresponding simulation setup to achieve the reported results.
650		0	_aEngineering.
650		0	_aElectronics.
650		0	_aSystems engineering.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aElectronics and Microelectronics, Instrumentation.
650	2	4	_aNanotechnology and Microengineering.
700	1		_aAmpadu, Paul. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781461409618
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4614-0962-5
912			_aZDB-2-ENG
999			_c100962 _d100962