000			03342nam a22004575i 4500
001			978-1-4614-0872-7
003			DE-He213
005			20140220083240.0
007			cr nn 008mamaa
008			111020s2012 xxu| s |||| 0|eng d
020			_a9781461408727 _9978-1-4614-0872-7
024	7		_a10.1007/978-1-4614-0872-7 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aAhuja, Sumit. _eauthor.
245	1	0	_aLow Power Design with High-Level Power Estimation and Power-Aware Synthesis _h[electronic resource] / _cby Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla.
264		1	_aNew York, NY : _bSpringer New York, _c2012.
300			_aXXII, 170p. 39 illus. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aIntroduction -- Related Work -- Background -- Architectural Selection using High Level Synthesis -- Statistical Regression Based Power Models -- Coprocessor Design Space Exploration Using High Level Synthesis -- Regression-based Dynamic Power Estimation for FPGAs -- High Level Simulation Directed RTL Power Estimation -- Applying Verification Collaterals for Accurate Power Estimation -- Power Reduction using High-Level Clock-gating -- Model-Checking to exploit Sequential Clock-gating -- System Level Simulation Guided Approach for Clock-gating -- Conclusions.
520			_aLow-power ASIC/FPGA based designs are important due to the need for extended battery life, reduced form factor, and lower packaging and cooling costs for electronic devices. These products require fast turnaround time because of the increasing demand for handheld electronic devices such as cell-phones, PDAs and high performance machines for data centers. To achieve short time to market, design flows must facilitate a much shortened time-to-product requirement. High-level modeling, architectural exploration and direct synthesis of design from high level description enable this design process. This book presents novel research techniques, algorithms,methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design. Integrates power estimation and reduction for high level synthesis, with low-power, high-level design; Shows specific techniques for ASICs as well as FPGA based SoC designs, allowing readers to evaluate and explore various possible alternatives; Covers techniques from RTL/gate-level to hardware software co-design.
650		0	_aEngineering.
650		0	_aComputer aided design.
650		0	_aSystems engineering.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aComputer-Aided Engineering (CAD, CAE) and Design.
700	1		_aLakshminarayana, Avinash. _eauthor.
700	1		_aShukla, Sandeep Kumar. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781461408710
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4614-0872-7
912			_aZDB-2-ENG
999			_c100939 _d100939