000			03410nam a22004695i 4500
001			978-1-4419-9976-4
003			DE-He213
005			20140220083234.0
007			cr nn 008mamaa
008			120130s2012 xxu| s |||| 0|eng d
020			_a9781441999764 _9978-1-4419-9976-4
024	7		_a10.1007/978-1-4419-9976-4 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aEggersglüß, Stephan. _eauthor.
245	1	0	_aHigh Quality Test Pattern Generation and Boolean Satisfiability _h[electronic resource] / _cby Stephan Eggersglüß, Rolf Drechsler.
264		1	_aBoston, MA : _bSpringer US, _c2012.
300			_aXVIII, 193p. 55 illus. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aPart I: Preliminaries and Previous Work -- Circuits and Testing -- Boolean Satisfiability -- ATPG Based on Boolean Satisfiability -- Part II: New SAT Techniques and their Application in ATPG -- Dynamic Clause Activation -- Circuit-based Dynamic Learning -- Part III: High Quality Delay Test Generation -- High Quality ATPG for Transition Faults -- Path Delay Fault Model -- Summary and Outlook.
520			_aThis book provides an overview of automatic test pattern generation (ATPG) and introduces novel techniques to complement classical ATPG, based on Boolean Satisfiability (SAT).  A fast and highly fault efficient SAT-based ATPG framework is presented which is also able to generate high-quality delay tests such as robust path delay tests, as well as tests with long propagation paths to detect small delay defects. The aim of the techniques and methodologies presented in this book is to improve SAT-based ATPG, in order to make it applicable in industrial practice. Readers will learn to improve the performance and robustness of the overall test generation process, so that the ATPG algorithm reliably will generate test patterns for most targeted faults in acceptable run time to meet the high fault coverage demands of industry. The techniques and improvements presented in this book provide the following advantages: Provides a comprehensive introduction to test generation and Boolean Satisfiability (SAT); Describes a highly fault efficient SAT-based ATPG framework; Introduces circuit-oriented SAT solving techniques, which make use of structural information and are able to accelerate the search process significantly; Provides SAT formulations for the prevalent delay faults models, in addition to the classical stuck-at fault model; Includes an industrial perspective on the state-of-the-art in the testing, along with SAT; two topics typically distinguished from each other.
650		0	_aEngineering.
650		0	_aComputer science.
650		0	_aElectronics.
650		0	_aSystems engineering.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aElectronics and Microelectronics, Instrumentation.
650	2	4	_aProcessor Architectures.
700	1		_aDrechsler, Rolf. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781441999757
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4419-9976-4
912			_aZDB-2-ENG
999			_c100610 _d100610