| 000 | 03139nam a22005055i 4500 | ||
|---|---|---|---|
| 001 | 978-1-4419-9660-2 | ||
| 003 | DE-He213 | ||
| 005 | 20140220083234.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 120614s2012 xxu| s |||| 0|eng d | ||
| 020 |
_a9781441996602 _9978-1-4419-9660-2 |
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| 024 | 7 |
_a10.1007/978-1-4419-9660-2 _2doi |
|
| 050 | 4 | _aTK7888.4 | |
| 072 | 7 |
_aTJFC _2bicssc |
|
| 072 | 7 |
_aTEC008010 _2bisacsh |
|
| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aMarković, Dejan. _eauthor. |
|
| 245 | 1 | 0 |
_aDSP Architecture Design Essentials _h[electronic resource] / _cby Dejan Marković, Robert W. Brodersen. |
| 264 | 1 |
_aBoston, MA : _bSpringer US : _bImprint: Springer, _c2012. |
|
| 300 |
_aXIV, 351 p. 603 illus., 452 illus. in color. _bonline resource. |
||
| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
||
| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
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| 490 | 1 | _aElectrical Engineering Essentials | |
| 505 | 0 | _aEnergy and Delay Models -- Circuit Optimization -- Architectural Techniques -- Architecture Flexibility -- Arithmetic for DSP -- CORDIC, Divider, Square Root -- Digital Filters -- Time-Frequency Analysis -- Data-Flow Graph Model -- Wordlength Optimization -- Architectural Optimization -- Simulink-Hardware Flow -- Multi-GHz Radio DSP -- Dedicated MHz-rate Decoders -- Flexible MHz-rate Decoder -- kHz-rate Neural Processors -- Brief Outlook. | |
| 520 | _aIn DSP Architecture Design Essentials, authors Dejan Marković and Robert W. Brodersen cover a key subject for the successful realization of DSP algorithms for communications, multimedia, and healthcare applications. The book addresses the need for DSP architecture design that maps advanced DSP algorithms to hardware in the most power- and area-efficient way. The key feature of this text is a design methodology based on a high-level design model that leads to hardware implementation with minimum power and area. The methodology includes algorithm-level considerations such as automated word-length reduction and intrinsic data properties that can be leveraged to reduce hardware complexity. From a high-level data-flow graph model, an architecture exploration methodology based on linear programming is used to create an array of architectural solutions tailored to the underlying hardware technology. The book is supplemented with online material: bibliography, design examples, CAD tutorials and custom software. | ||
| 650 | 0 | _aEngineering. | |
| 650 | 0 | _aComputer science. | |
| 650 | 0 | _aComputer engineering. | |
| 650 | 0 | _aSystems engineering. | |
| 650 | 1 | 4 | _aEngineering. |
| 650 | 2 | 4 | _aCircuits and Systems. |
| 650 | 2 | 4 | _aSignal, Image and Speech Processing. |
| 650 | 2 | 4 | _aElectrical Engineering. |
| 650 | 2 | 4 | _aProcessor Architectures. |
| 700 | 1 |
_aBrodersen, Robert W. _eauthor. |
|
| 710 | 2 | _aSpringerLink (Online service) | |
| 773 | 0 | _tSpringer eBooks | |
| 776 | 0 | 8 |
_iPrinted edition: _z9781441996596 |
| 830 | 0 | _aElectrical Engineering Essentials | |
| 856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/978-1-4419-9660-2 |
| 912 | _aZDB-2-ENG | ||
| 999 |
_c100590 _d100590 |
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