000			03093nam a22004575i 4500
001			978-1-4419-9313-7
003			DE-He213
005			20140220083233.0
007			cr nn 008mamaa
008			111007s2012 xxu| s |||| 0|eng d
020			_a9781441993137 _9978-1-4419-9313-7
024	7		_a10.1007/978-1-4419-9313-7 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aFu, Bo. _eauthor.
245	1	0	_aError Control for Network-on-Chip Links _h[electronic resource] / _cby Bo Fu, Paul Ampadu.
250			_a1.
264		1	_aNew York, NY : _bSpringer New York, _c2012.
300			_aXI, 151p. 108 illus. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aIntroduction -- Solutions to Improve the Reliability of On-Chip Interconnects -- Networks-on-Chip (NoC) -- Error Control Coding for On-Chip Interconnects -- Energy Efficient Error Control Implementation -- Combining Error Control Codes with Crosstalk Reduction.
520			_aAs technology scales into nanoscale regime, it is impossible to guarantee the perfect hardware design. Moreover, if the requirement of 100% correctness in hardware can be relaxed, the cost of manufacturing, verification, and testing will be significantly reduced. Many approaches have been proposed to address the reliability problem of on-chip communications. This book focuses on the use of error control codes (ECCs) to improve on-chip interconnect reliability. Coverage includes detailed description of key issues in NOC error control faced by circuit and system designers, as well as practical error control techniques to minimize the impact of these errors on system performance. Provides a detailed background on the state of error control methods for on-chip interconnects; Describes the use of more complex concatenated codes such as Hamming Product Codes with Type-II HARQ, while emphasizing integration techniques for on-chip interconnect links; Examines energy-efficient techniques for integrating multiple error control methods in on-chip interconnects; Introduces various design techniques to tradeoff the reliability and energy consumption of on-chip interconnects, including implementation of low link swing voltage and dynamic voltage scaling with error control codes, combination of Hamming product codes with type-II hybrid ARQ, and configurable error control codes implementation.
650		0	_aEngineering.
650		0	_aComputer aided design.
650		0	_aSystems engineering.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aComputer-Aided Engineering (CAD, CAE) and Design.
700	1		_aAmpadu, Paul. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781441993120
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4419-9313-7
912			_aZDB-2-ENG
999			_c100570 _d100570