000			03170nam a22004575i 4500
001			978-1-4419-6778-7
003			DE-He213
005			20140220083233.0
007			cr nn 008mamaa
008			111014s2012 xxu| s |||| 0|eng d
020			_a9781441967787 _9978-1-4419-6778-7
024	7		_a10.1007/978-1-4419-6778-7 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aSoudris, Dimitrios. _eeditor.
245	1	0	_aScalable Multi-core Architectures _h[electronic resource] : _bDesign Methodologies and Tools / _cedited by Dimitrios Soudris, Axel Jantsch.
250			_a1.
264		1	_aNew York, NY : _bSpringer New York, _c2012.
300			_aXIV, 223 p. 109 illus. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aPart I: HS/SW/ Building Blocks: Architecture, Methods, and Techniques -- 1. Memory Architecture and Management in an NoC Platform -- 2. Application-Specific Multi-Threaded Dynamic Memory Management -- 3. Power Management Architecture in McNoC -- 4. ASIP Exploration and Design -- Part II: System-level Exploration -- 5. System Exploration -- 6. MPA: Parallelization Made Easy -- Part III: Industrial Applications -- 7. MPSoC Architecture Performance Analysis for Agile SDR Radio Applications -- 8. Application of the MOSART Flow on the WiMAX (802.16e) PHY.
520			_aAs Moore’s law continues to unfold, two important trends have recently emerged. First, the growth of chip capacity is translated into a corresponding increase of number of cores. Second, the parallalization of the computation and 3D integration technologies lead to distributed memory architectures. This book provides a current snapshot of industrial and academic research, conducted as part of the European FP7 MOSART project, addressing urgent challenges in many-core architectures and application mapping.  It addresses the architectural design of many core chips, memory and data management, power management, design and programming methodologies. It also describes how new techniques have been applied in various industrial case studies. Describes trends towards distributed memory architectures and distributed power management; Integrates Network on Chip with distributed, shared memory architectures; Demonstrates novel design methodologies and frameworks for multi-core design space exploration; Shows how midlleware services (dynamic data management) can be integrated into and support by the platform.
650		0	_aEngineering.
650		0	_aComputer aided design.
650		0	_aSystems engineering.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aComputer-Aided Engineering (CAD, CAE) and Design.
700	1		_aJantsch, Axel. _eeditor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781441967770
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4419-6778-7
912			_aZDB-2-ENG
999			_c100532 _d100532