Fundamentals of VLSI Testing -- Power Issues During Test -- Low-Power Test Pattern Generation -- Power-Aware Design-for-Test -- Power-Aware Test Data Compression and BIST -- Power-Aware System-Level Test Planning -- Low-Power Design Techniques and Test Implications -- Test Strategies for Multivoltage Designs -- Test Strategies for Gated Clock Designs -- Test of Power Management Structures -- EDA Solution for Power-Aware Design-for-Test.

Power-Aware Testing and Test Strategies for Low-Power Devices Edited by: Patrick Girard, Research Director, CNRS / LIRMM, France Nicola Nicolici, Associate Professor, McMaster University, Canada Xiaoqing Wen, Professor, Kyushu Institute of Technology, Japan Managing the power consumption of circuits and systems is now considered as one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low-power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and Electronic Design Automation (EDA) solutions for testing low-power devices. The first comprehensive book on power-aware test for (low-power) circuits and systems Shows readers how low-power devices can be tested safely without affecting yield and reliability Includes necessary background information on design-for-test and low-power design Covers in detail power-constrained test techniques, including power-aware automatic test pattern generation, design-for-test, built-in self-test and test compression Presents state-of-the-art industrial practices and EDA solutions