Designing 2D and 3D Network-on-Chip Architectures (Record no. 91962)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03157nam a22004935i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-1-4614-4274-5 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20140220082457.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 131008s2014 xxu| s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781461442745 |
| -- | 978-1-4614-4274-5 |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1007/978-1-4614-4274-5 |
| Source of number or code | doi |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TK7888.4 |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | TJFC |
| Source | bicssc |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | TEC008010 |
| Source | bisacsh |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3815 |
| Edition number | 23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Tatas, Konstantinos. |
| Relator term | author. |
| 245 10 - TITLE STATEMENT | |
| Title | Designing 2D and 3D Network-on-Chip Architectures |
| Medium | [electronic resource] / |
| Statement of responsibility, etc | by Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch. |
| 264 #1 - | |
| -- | New York, NY : |
| -- | Springer New York : |
| -- | Imprint: Springer, |
| -- | 2014. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | XIII, 265 p. 144 illus., 79 illus. in color. |
| Other physical details | online resource. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Part I: Network-on-Chip Design Methodology -- Network-on-Chip Technology: A Paradigm Shift -- NoC Modeling and Topology Exploration -- Communication Architecture -- Power and Thermal Effects and Management -- NoC-based System Integration -- NoC Verification and Testing -- The Spidergon STNoC -- Middleware Memory Management in NoC -- On Designing 3-D Platforms -- The SYSMANTIC NoC Design and Prototyping Framework -- Part II: Suggested Projects.- Projects on Network-on Chip. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliabilty. Case studies are used to illuminate new design methodologies. · Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect; · Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance; · Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer science. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Electronics. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Systems engineering. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Electronics and Microelectronics, Instrumentation. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Processor Architectures. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Siozios, Kostas. |
| Relator term | author. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Soudris, Dimitrios. |
| Relator term | author. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Jantsch, Axel. |
| Relator term | author. |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY | |
| Title | Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Display text | Printed edition: |
| International Standard Book Number | 9781461442738 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://dx.doi.org/10.1007/978-1-4614-4274-5 |
| 912 ## - | |
| -- | ZDB-2-ENG |
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