On and Off-Chip Crosstalk Avoidance in VLSI Design (Record no. 110282)

000 -LEADER
fixed length control field 03979nam a22004575i 4500
001 - CONTROL NUMBER
control field 978-1-4419-0947-3
003 - CONTROL NUMBER IDENTIFIER
control field DE-He213
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20140220084503.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
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fixed length control field 100301s2010 xxu| s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781441909473
-- 978-1-4419-0947-3
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.1007/978-1-4419-0947-3
Source of number or code doi
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number TK7888.4
072 #7 - SUBJECT CATEGORY CODE
Subject category code TJFC
Source bicssc
072 #7 - SUBJECT CATEGORY CODE
Subject category code TEC008010
Source bisacsh
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3815
Edition number 23
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Duan, Chunjie.
Relator term author.
245 10 - TITLE STATEMENT
Title On and Off-Chip Crosstalk Avoidance in VLSI Design
Medium [electronic resource] /
Statement of responsibility, etc by Chunjie Duan, Brock J. LaMeres, Sunil P. Khatri.
264 #1 -
-- Boston, MA :
-- Springer US,
-- 2010.
300 ## - PHYSICAL DESCRIPTION
Extent XXIV, 240p. 600 illus., 300 illus. in color.
Other physical details online resource.
336 ## -
-- text
-- txt
-- rdacontent
337 ## -
-- computer
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-- rdamedia
338 ## -
-- online resource
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-- rdacarrier
347 ## -
-- text file
-- PDF
-- rda
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note On-Chip Crosstalk and Avoidance -- of On-Chip Crosstalk Avoidance -- Preliminaries to On-chip Crosstalk -- Memoryless Crosstalk Avoidance Codes -- CODEC Designs for Memoryless Crosstalk Avoidance Codes -- Memory-based Crosstalk Avoidance Codes -- Multi-valued Logic Crosstalk Avoidance Codes -- Summary of On-Chip Crosstalk Avoidance -- Off-Chip Crosstalk and Avoidance -- to Off-Chip Crosstalk -- Package Construction and Electrical Modeling -- Preliminaries and Terminology -- Analytical Model for Off-Chip Bus Performance -- Optimal Bus Sizing -- Bus Expansion Encoder -- Bus Stuttering Encoder -- Impedance Compensation -- Future Trends and Applications -- Summary of Off-Chip Crosstalk Avoidance.
520 ## - SUMMARY, ETC.
Summary, etc On- and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus traces. Capacitive crosstalk in on-chip busses becomes significant with shrinking feature sizes of VLSI fabrication processes, while inductive cross-talk becomes a problem for busses with high off-chip data transfer rates. The presence of crosstalk greatly limits the speed and increases the power consumption of an IC design. This book presents approaches to avoid crosstalk in both on-chip as well as off-chip busses. These approaches allow the user to trade off the degree of crosstalk mitigation against the associated implementation overheads. In this way, a continuum of techniques is presented, which help improve the speed and power consumption of the bus interconnect. These techniques encode data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption. In particular, this book: Presents novel ways to combine chip and package design, reducing off-chip crosstalk so that VLSI systems can be designed to operate significantly faster; Provides a comprehensive set of bus crosstalk cancellation techniques, both memoryless and memory-based; Provides techniques to design extremely efficient CODECs for crosstalk cancellation; Provides crosstalk cancellation approaches for multi-valued busses; Offers a battery of approaches for a VLSI designer to use, depending on the amount of crosstalk their design can tolerate, and the amount of area overhead they can afford.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Engineering.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer aided design.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Systems engineering.
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Engineering.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Circuits and Systems.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer-Aided Engineering (CAD, CAE) and Design.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name LaMeres, Brock J.
Relator term author.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Khatri, Sunil P.
Relator term author.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
773 0# - HOST ITEM ENTRY
Title Springer eBooks
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Display text Printed edition:
International Standard Book Number 9781441909466
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier http://dx.doi.org/10.1007/978-1-4419-0947-3
912 ## -
-- ZDB-2-ENG

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