Post-Silicon and Runtime Verification for Modern Processors (Record no. 105918)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03207nam a22004695i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-1-4419-8034-2 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20140220083726.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 101125s2011 xxu| s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781441980342 |
| -- | 978-1-4419-8034-2 |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1007/978-1-4419-8034-2 |
| Source of number or code | doi |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TK7888.4 |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | TJFC |
| Source | bicssc |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | TEC008010 |
| Source | bisacsh |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3815 |
| Edition number | 23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Wagner, Ilya. |
| Relator term | author. |
| 245 10 - TITLE STATEMENT | |
| Title | Post-Silicon and Runtime Verification for Modern Processors |
| Medium | [electronic resource] / |
| Statement of responsibility, etc | by Ilya Wagner, Valeria Bertacco. |
| 264 #1 - | |
| -- | Boston, MA : |
| -- | Springer US, |
| -- | 2011. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | XVII, 224p. 50 illus. |
| Other physical details | online resource. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Verification of a Modern Processor -- The Verification Universe -- Test Generation and Response Evaluation for Processors Cores in Post-Silicon -- Post-Silicon Verification of Multi-Core Processors -- Run-Time Verification Through Hardware Patching and Error Avoidance -- The Future of Post-Silicon Verification. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | Post-Silicon and Run-Time Verification for Modern Processors surveys the state of the art and evolving directions in post-silicon and runtime verification. The volume gives an overview of the state of the art in verification, particularly current post-silicon methodologies in use in the industry, both for the domain of processor pipeline design and for memory subsystems. There is also a thorough presentation of several new post-silicon verification solutions aimed at boosting the verification coverage of modern processors. The presentation of runtime verification solutions follows a similar approach. This is an area of processor design that is still in its early stages of exploration and could help accomplish the ultimate goal of complete correctness guarantees for microprocessor-based computation. The book also: · Addresses an area of hardware verification that is growing both in industry and academia · Covers hardware patching and error avoidance · Discusses multi-core processors with test generation and response evaluation The authors conclude the book with a look towards the future of late-stage verification and its growing role in the processor life-cycle. Post-Silicon and Run-Time Verification for Modern Processors will be a valuable book for researchers and engineers working in electrical engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer hardware. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer aided design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Systems engineering. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer Hardware. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer-Aided Engineering (CAD, CAE) and Design. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Bertacco, Valeria. |
| Relator term | author. |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY | |
| Title | Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Display text | Printed edition: |
| International Standard Book Number | 9781441980335 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://dx.doi.org/10.1007/978-1-4419-8034-2 |
| 912 ## - | |
| -- | ZDB-2-ENG |
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