Low Power Design with High-Level Power Estimation and Power-Aware Synthesis (Record no. 100939)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03342nam a22004575i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-1-4614-0872-7 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20140220083240.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 111020s2012 xxu| s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781461408727 |
| -- | 978-1-4614-0872-7 |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1007/978-1-4614-0872-7 |
| Source of number or code | doi |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TK7888.4 |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | TJFC |
| Source | bicssc |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | TEC008010 |
| Source | bisacsh |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3815 |
| Edition number | 23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Ahuja, Sumit. |
| Relator term | author. |
| 245 10 - TITLE STATEMENT | |
| Title | Low Power Design with High-Level Power Estimation and Power-Aware Synthesis |
| Medium | [electronic resource] / |
| Statement of responsibility, etc | by Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla. |
| 264 #1 - | |
| -- | New York, NY : |
| -- | Springer New York, |
| -- | 2012. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | XXII, 170p. 39 illus. |
| Other physical details | online resource. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Introduction -- Related Work -- Background -- Architectural Selection using High Level Synthesis -- Statistical Regression Based Power Models -- Coprocessor Design Space Exploration Using High Level Synthesis -- Regression-based Dynamic Power Estimation for FPGAs -- High Level Simulation Directed RTL Power Estimation -- Applying Verification Collaterals for Accurate Power Estimation -- Power Reduction using High-Level Clock-gating -- Model-Checking to exploit Sequential Clock-gating -- System Level Simulation Guided Approach for Clock-gating -- Conclusions. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | Low-power ASIC/FPGA based designs are important due to the need for extended battery life, reduced form factor, and lower packaging and cooling costs for electronic devices. These products require fast turnaround time because of the increasing demand for handheld electronic devices such as cell-phones, PDAs and high performance machines for data centers. To achieve short time to market, design flows must facilitate a much shortened time-to-product requirement. High-level modeling, architectural exploration and direct synthesis of design from high level description enable this design process. This book presents novel research techniques, algorithms,methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design. Integrates power estimation and reduction for high level synthesis, with low-power, high-level design; Shows specific techniques for ASICs as well as FPGA based SoC designs, allowing readers to evaluate and explore various possible alternatives; Covers techniques from RTL/gate-level to hardware software co-design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer aided design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Systems engineering. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer-Aided Engineering (CAD, CAE) and Design. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Lakshminarayana, Avinash. |
| Relator term | author. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Shukla, Sandeep Kumar. |
| Relator term | author. |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY | |
| Title | Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Display text | Printed edition: |
| International Standard Book Number | 9781461408710 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://dx.doi.org/10.1007/978-1-4614-0872-7 |
| 912 ## - | |
| -- | ZDB-2-ENG |
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